1. Field of the Invention
The present invention generally relates to a method (and resultant structure) of forming a semiconductor device, and more particularly to a method (and resultant structure) of forming a dual damascene interconnection.
2. Description of the Related Art
Currently, it is difficult to adequately line contacts for copper filling at contact dimensions below 280 nm, and to line contacts reliably below contact opening sizes of less than 320 nm. This presents a major challenge to dynamic random access memory back-end-of-line (DRAM BEOL) processing that would like to migrate to a copper back-end in the near future.
Additionally, in the conventional methods, there are a large number of types of conducting materials that must be implemented in a BEOL process.
Further, the conventional methods require a separate method for producing DRAM BEOL and a separate method for producing the logic BEOL so that different manufacturing lines are required to produce either DRAM or logic with the same type and number of tools.
Finally, the conventional methods typically attempt to fill substantially both small and large structures with copper, thereby requiring additional and costly processing such as multiple CVD and advanced PVD diffusion barriers and liners which enable Cu plating.